`timescale 1 ns / 1 ps
module tb_cal16;
reg [15:0] a,b;
wire [15:0] sum; 
integer seed1,seed2;


reg clk;
initial clk=0;
always # 10clk=~clk;


cla16 my_cla(a,b,sum);

initial  seed1=2;
initial  seed2=3;
always @(posedge clk)
        a = {$random(seed1)} %1024;
always @(posedge clk)
        b = {$random(seed2)} %1024;
        
endmodule